Abstract - A. Cerdeira
Double-Gate (DG) transistors are considered a very attractive option of the Silicon-On-Insulator (SOI) MOSFETs to improve the performance of CMOS SOI devices. Some advantages are: reduced short channel effects; lower parasitic capacitances; increased circuit speed; stronger control of the channel by the gate; reduced drain-induced barrier lowering, threshold voltage roll-off and off-state leakage. DG transistors are very attractive for applications in low power and low voltage digital and analog integrated circuits.
The demand of an accurate and CAD compatible compact model for DG MOSFETs is a really urgent task, reason why many researchers are dealing with it. The main problem for modeling fully depleted DG devices is that the potential at the surface and the potential at the middle of the silicon layer are related and can not be treated independently one from the other. In addition, the electric field and gate voltage of the device as function of these potentials are expressed by transcendental equations that do not have analytical solution.
In this talk we present a new compact analytical model for symmetric double-gate MOSFETs transistors that for the first time considers the doping concentration of the silicon layer variable from undoped to 3x1018 cm-3. First, the core model for long channel devices is presented, which was later complemented in order to include the followings short channel effects: VT variation with channel length reduction and DIBL; velocity saturation effects; series resistance; channel shortening and subthreshold slope degradation. The model for short channel devices requires only six parameters to extract. Validation using 2D simulation for both high and low doped devices is presented. Finally, modeled and experimental measurements of FinFETs working in the temperature range from 20 °C to 200 °C are compared.