Semiconductor Reliability Topics for Advanced CMOS Technologies
As we continue the relentless drive towards smaller semiconductor device feature sizes and higher levels of integration at the chip level, it has become increasingly evident that a judicious review and a very complete understanding of the reliability mechanisms that contribute to the degradation of each of the technology elements will be crucial for the successful development of the most advanced leading edge technologies. The increased device count and process complexity, coupled with ever decreasing margins in voltage, geometry and the incorporation of new material systems like high and low k dielectrics, stress/strain layers, and other limiting factors will be discussed from the reliability perspective. A closer look will be given to Hot Carriers, Bias Temperature Instabilities and statistical variations (process and geometric). This talk will present the reliability issues driven by the latest trends and state of the art in semiconductor fabrication; it will also present the considerations necessary with a practical approach to the qualification methodology required for advanced CMOS technologies while providing a review of the specifications and implications of the above mentioned reliability mechanisms. The impact of reliability induced parameter degradation and the mitigation of these effects will be studied for practical circuits through the analysis of switching behavior and SRAM applications. The characterization, models and methodology will be put in the required perspective for the successful technology transfer of leading edge technologies to a manufacturing environment.